This invention relates to a digital phase-locked loop comprising a phase comparator, a controllable oscillator whose output signal is compared with an input signal in the phase comparator, and a loop filter preceding the oscillator, which filter comprises a clocked input register for storing the last phase-measuring value of the phase comparator, and an integrator which comprises a clocked register whose output signal is fed back to the register input.
Phase-locked loops (PLLs) present a problem in the absence of the input signal or in the case of a distrubed input signal to the phase comparator. In that event, when this signal is compared in the phase comparator with the output signal of the controllable oscillator, the phase comparator supplies an erroneous or accidental output signal which causes the frequency of the controllable oscillator to fluctuate or to vary between its minimum and maximum frequency values. These effects are undesirable. In contrast, it is desirable for the oscillator to oscillate at its rated frequency.
For an analog phase-locked, loop a circuit arrangement is known from U.S. Pat. No. 3,882,412 which in the absence of the input signal of the phase comparator attempts to keep the oscillator at the last adjusted frequency. This is effected by means of a digital circuit which stores the last, actual measured value and supplies it to the phase-locked loop in the absence of the input signal. However, such an arrangement is not suitable for digital loop filters. This applies particularly to digital loop filters having a recursive function.